wafer.space Community

@RebelMike the 1xp5 boards have arrived. Pretty sure some will be bonded shortly. @Tim Edwards I think yours and @Greg will also be bonded in this run.

2

Hi Andrew @Andrew Wingate and Tim @Tim 'mithro' Ansell , I have heard from Tim that there is a good method verifying the wire bond connections. Would you mind helping pointing me to the correct location where this verification method is discussed. This would help a lot in our chip debugging. Many thanks.

Andrew Wingate

@RebelMike the 1xp5 boards have arrived. Pretty sure some will be bonded shortly. @Tim Edwards I think yours and @Greg will also be bonded in this run.

Was the ground fill on the region between the die and the pins intentional? I think that was blocked originally. And there was some discussion of putting soldermask in that region so the vias were covered, is that still something that we think we should try?

Oh as I see this now if they're done by JLCPCB, I'd propose using their serialization service that'll give per-individual silkscreen serials in plain text (+ (QR/datamatrix)), though for proper traceability beyond the bondhouse the die sorter would probably have to place the dies directly onto the COB and electronically record what specific die got placed onto that serial number COB?

RebelMike

Was the ground fill on the region between the die and the pins intentional? I think that was blocked originally. And there was some discussion of putting soldermask in that region so the vias were covered, is that still something that we think we should try?

Iirc we'd need those vias covered at the top or fully open to prevent air bubbles inside from going up through the encapsulation.

xianglin_pu

Hi Andrew @Andrew Wingate and Tim @Tim 'mithro' Ansell , I have heard from Tim that there is a good method verifying the wire bond connections. Would you mind helping pointing me to the correct location where this verification method is discussed. This would help a lot in our chip debugging. Many thanks.

ESD diode of the pad can be easily checked for presence once you have a working GND and a working VDD pad.

2:18 p.m.

Iirc you just carefully diode test with pad voltage below GND to see the diode to GND, and above VDD to see the diode to VDD.

namibj

ESD diode of the pad can be easily checked for presence once you have a working GND and a working VDD pad.

Thanks for the suggestion it’s good idea to check the bonding by testing the ESD diode. I am not sure the method mentioned by Tim is same as this, or there are other method verifying it (physically or electrically)

AFAIK the esd diode was the suggested check of bonding, shy of any testability instrumentation in the chip itself.

1

xianglin_pu

Hi Andrew @Andrew Wingate and Tim @Tim 'mithro' Ansell , I have heard from Tim that there is a good method verifying the wire bond connections. Would you mind helping pointing me to the correct location where this verification method is discussed. This would help a lot in our chip debugging. Many thanks.

Ooh, I don't think it has been talked about much in this discord, most of the conversation was in person when we were in China. It seems that @namibj has filled you in. Let me know if you have any other questions.

RebelMike

Was the ground fill on the region between the die and the pins intentional? I think that was blocked originally. And there was some discussion of putting soldermask in that region so the vias were covered, is that still something that we think we should try?

It did have a no fill region. This version was the one that I went in and relaxed some of the clearances and to do so, I needed to delete it for a moment as KiCad didn't allow me to select anything under it when it was there. After I finished I hit refill and it filled everywhere, since we had reduced this to 2 layers I thought the extra pour and ground wouldn't hurt anything so I left it. -# For future reference, you're able to add keepout areas to the footprint itself and then you don't get the selection issues I was running into (I assume you did that last because of the same issues?)

1

Andrew Wingate

It did have a no fill region. This version was the one that I went in and relaxed some of the clearances and to do so, I needed to delete it for a moment as KiCad didn't allow me to select anything under it when it was there. After I finished I hit refill and it filled everywhere, since we had reduced this to 2 layers I thought the extra pour and ground wouldn't hurt anything so I left it. -# For future reference, you're able to add keepout areas to the footprint itself and then you don't get the selection issues I was running into (I assume you did that last because of the same issues?)

Ah cool - yeah I don't think it should cause a problem, just wondered how it ended up like that

1

namibj

Oh as I see this now if they're done by JLCPCB, I'd propose using their serialization service that'll give per-individual silkscreen serials in plain text (+ (QR/datamatrix)), though for proper traceability beyond the bondhouse the die sorter would probably have to place the dies directly onto the COB and electronically record what specific die got placed onto that serial number COB?

We did have another version where they did the serial numbers properly, not sure what happened this go.

Andrew Wingate

We did have another version where they did the serial numbers properly, not sure what happened this go.

Did you select the option in the interface?

I was using locking to resolve the not being able to select things problems, I feel like that is a regression in KiCAD 10?

RebelMike

I was using locking to resolve the not being able to select things problems, I feel like that is a regression in KiCAD 10?

Oh? Could be?

Andrew Wingate

It did have a no fill region. This version was the one that I went in and relaxed some of the clearances and to do so, I needed to delete it for a moment as KiCad didn't allow me to select anything under it when it was there. After I finished I hit refill and it filled everywhere, since we had reduced this to 2 layers I thought the extra pour and ground wouldn't hurt anything so I left it. -# For future reference, you're able to add keepout areas to the footprint itself and then you don't get the selection issues I was running into (I assume you did that last because of the same issues?)

You can mask object types and layers from view and mouse interaction in kicad. Those two classifications are orthogonal.

namibj

Did you select the option in the interface?

Everything should have been the same. Again, not sure exactly what happened. We only got a few as these are the first ones for that form factor so should be ok. We'll get it next time. I forgot about the type selection stuff. Good call

Yeah they do caution it's supposedly a best-effort thing. I guess if you can take the day of delay you can do advanced instructions and tell them to complain if the serials somehow don't work.

Andrew Wingate

Ooh, I don't think it has been talked about much in this discord, most of the conversation was in person when we were in China. It seems that @namibj has filled you in. Let me know if you have any other questions.

I see, thanks for letting me know. I though there is a standard criteria you are using to determine if a wire is connected (physically or electrically) Since I am trying to verify if bonding is correct, chip is functional and hopefully proceed with more units packaged. (edited)

So what we did when we were just testing with a multimeter was to apply 3.3v to VSS Then we would go around the other pins and we saw the voltage across with the diode drop. If there was no connection, you would read nothing. The VDD pads showed up a little differently because there was a decoupling cap on the wire as well. But at the end of the day, you are correct, we can really only when if a wire is electrically connected. To verify things actually work how you desire, you'll have to come up with your own testing procedures. I think what @Tim 'mithro' Ansell is asking most specifically is: Does your silicon work as expected and good enough you want them all packaged? -# sorry meant to have this as reply to @xianglin_pu (edited)

1

Andrew Wingate

So what we did when we were just testing with a multimeter was to apply 3.3v to VSS Then we would go around the other pins and we saw the voltage across with the diode drop. If there was no connection, you would read nothing. The VDD pads showed up a little differently because there was a decoupling cap on the wire as well. But at the end of the day, you are correct, we can really only when if a wire is electrically connected. To verify things actually work how you desire, you'll have to come up with your own testing procedures. I think what @Tim 'mithro' Ansell is asking most specifically is: Does your silicon work as expected and good enough you want them all packaged? -# sorry meant to have this as reply to @xianglin_pu (edited)

That makes sense, thanks for clarifying. When do you need our response on bonding the remaining units ?

xianglin_pu

That makes sense, thanks for clarifying. When do you need our response on bonding the remaining units ?

Don't use my opinion to judge anything too specifically, but I would say there isn't a super huge rush? Deadline would be enough time the wirebonders get done before we want them for Run#2

I'm really interested to see how these work for you all though. Please share when you're doing your tests and have one working!

1

@Andrew Wingate Do you know what the difference is between the "COB v1" and "COB v2+" adapter for the bond tester card ?

tnt

@Andrew Wingate Do you know what the difference is between the "COB v1" and "COB v2+" adapter for the bond tester card ?

Can you be a little more specific, I'm not sure I know what the bond tester card is?

The automatic bond tester jig thingie

9:47 p.m.

Can't remember who made it

tnt

The automatic bond tester jig thingie

Oh haha, yes, that would be @Lauri I think the biggest difference is there was a v1 that used some multiplexers that could not be sourced easily. The second version used new ones that were more readily available. You're referring to this thing yes? -# I should get better about sharing pictures, isn't that right @kris ;)

Andrew Wingate

Oh haha, yes, that would be @Lauri I think the biggest difference is there was a v1 that used some multiplexers that could not be sourced easily. The second version used new ones that were more readily available. You're referring to this thing yes? -# I should get better about sharing pictures, isn't that right @kris ;)

the more the merrier :p

1

@Andrew Wingate Yes this thing.

1

tnt

@Andrew Wingate Yes this thing.

I can try to answer some questions

I have a base board r1 same as the picture but then I got two daugther boards, one with a COBv1 sticker and one with a COBv2+ sticker. (edited)

tnt

I have a base board r1 same as the picture but then I got two daugther boards, one with a COBv1 sticker and one with a COBv2+ sticker. (edited)

I will have to defer to @Lauri on this one. It's currently the middle of the night there. The only COB differences that I am aware of, is the first ones he was testing were some of the originals that had the missing trace on the AUX_VDD pin. Beyond that, I left right before these came back from the PCB fab and have not had much involvement.

tnt

I have a base board r1 same as the picture but then I got two daugther boards, one with a COBv1 sticker and one with a COBv2+ sticker. (edited)

I just remembered there is a little i2c memory module on the daughter board. I bet he was reading that to choose what program to run for a pass/fail thing without having to reflash or something? This is a guess, but an educated one.

Oh yeah maybe. Because PCB look identical. So different programming might make more sense.

10:11 p.m.

I'll wait for them to confirm.

1

tnt

Oh yeah maybe. Because PCB look identical. So different programming might make more sense.

Yes, the adapter boards are the same, only the EEPROM configuration differs. The v1 COB adapter skips the missing trace pad check. I've attached a picture showing which black COB is v1 and which is v2.

@Lauri Thanks, makes perfect sense. I had forgotten there was a track missing

Is there anyone looking for a full stack and ai engineer?

@Lauri - This is pretty cool!

3

1

Hey all, For the first run, originally we thought we would only have a single die size, so only had a single size tape. I would like to give myself as much clearance as possible to land the dies in the tape, hopefully we'll be able to do this blind saving the time of having a camera step. Any PNP should be able to pick up the components no problem. Does anyone have opinions on 0.5mm clearance on all sides?

Is the camera a throughput issue or an engineering complexity issue?

namibj

Is the camera a throughput issue or an engineering complexity issue?

Throughput

4:50 a.m.

Again, not really an issue, but at 50k dies the seconds add up.

@Andrew Wingate - I just randomly found https://www.digikey.com/en/articles/how-to-improve-chiplet-and-wlcsp-assembly-yields-using-precision-tape-and-reel-carriers while searching for information about tape and reel for through hole headers

1

Tim 'mithro' Ansell

@Andrew Wingate - I just randomly found https://www.digikey.com/en/articles/how-to-improve-chiplet-and-wlcsp-assembly-yields-using-precision-tape-and-reel-carriers while searching for information about tape and reel for through hole headers

I've also looked through our conversations to see what kind of material they used, I didn't find an answer. We can ask what they offer when we talk again.

Andrew Wingate

Hey all, For the first run, originally we thought we would only have a single die size, so only had a single size tape. I would like to give myself as much clearance as possible to land the dies in the tape, hopefully we'll be able to do this blind saving the time of having a camera step. Any PNP should be able to pick up the components no problem. Does anyone have opinions on 0.5mm clearance on all sides?

Had you considered attaching them to COBs (at least for those customers that want COB service) (but not yet bonding the pad ring) directly from the sorter?

namibj

Had you considered attaching them to COBs (at least for those customers that want COB service) (but not yet bonding the pad ring) directly from the sorter?

That would for sure have to be a future rev thing. I'm not even sure how viable that would even be though. There is some kind of glue that attaches them to the cob and I'm sure there is some kind of pot life that would be exceeded under most circumstances. Thanks for the thought, I've tried to think of things along these lines, just don't think it will work from what we know at the moment.

Hi all, I'm wondering if anyone sees the same thing as I do here.

Andrew Wingate

That would for sure have to be a future rev thing. I'm not even sure how viable that would even be though. There is some kind of glue that attaches them to the cob and I'm sure there is some kind of pot life that would be exceeded under most circumstances. Thanks for the thought, I've tried to think of things along these lines, just don't think it will work from what we know at the moment.

My first thought on the glue would be to use a simple static mixer nozzle dispensing freshly mixed epoxy of a nominal pot life somewhere around 5~30 minutes, but a thermoset might be better by disconnecting pot life from hardening speed. I'm sure there are practical solutions from the industry for the task of "die attach". Upon re-reading https://discord.com/channels/1361349522684510449/1361349523724570941/1506916734181834773 I'm not sure @Max Vallone meant they'll try in-house pillars on Run2 dies (~4 months until I would expect actionable results reports) or if there's consideration to try and verify/confirm functionality several days ahead of the Run2 GDS deadline. Why does that matter?: Depending on the extent of "bumping" treatment that needs to be done to the die (well, especially if it doesn't), skipping the T&R packaging between the "pick from stretched film" and "optically align die pads to first routing/contact layer of fan-out" (if it's the FPC-attached-via-ACF technique I suggested for prototyping and low-cost applications, this is done by looking at the die through the FPC while aligning before gently pressing them together to lock in the alignment during the travel to the hot press) might be desirable.

Andrew Wingate

@RebelMike the 1xp5 boards have arrived. Pretty sure some will be bonded shortly. @Tim Edwards I think yours and @Greg will also be bonded in this run.

Just to double check this has been communicated correctly: this was based on the original 1x1 CoB, so the die should be bonded with the Wafer Space logo in the opposite corners.

Tim 'mithro' Ansell

@Lauri - This is pretty cool!

Where is that app ?

tnt

Where is that app ?

This was just a widget prototype I was experimenting with. It will need a bit more work before I can release it for use. Shouldn't take long, i'll keep you informed.

@Leo Moser (mole99) and everyone, I have updated the symbol and everything on the motherboards. They now show net labels and everything where and how you would expect them.

4

Andrew Wingate

@Leo Moser (mole99) and everyone, I have updated the symbol and everything on the motherboards. They now show net labels and everything where and how you would expect them.

Can confirm, the pins are now mapped correctly. Thanks, Andrew!

1

interesting approach to avoid wire bonding (from https://opg.optica.org/oe/fulltext.cfm?uri=oe-34-11-20833)

1

Lauri started a thread. 2026-06-07 8:12 a.m.

BreakingTaps

interesting approach to avoid wire bonding (from https://opg.optica.org/oe/fulltext.cfm?uri=oe-34-11-20833)

Also TAB (tape automated bonding), for being relatively low-tech.

@BreakingTaps do you have any idea yet for selectively painting the exposed guard ring of Run1 dies so regular plating would grow just the pads up? I'll try to make a https://www.youtube.com/watch?v=MgQbPdiuUTw in around 1~2 months I guess, but the best plan there is for the time being a way to hold a fine hollow needle and to do computer vision alignment of flip chip die to FPC. But I'd think a litho process for separating the guard ring would be better than a mechanical painting one. An idea I have for the TT style would be to allow on-tile flip chip pads that could be bonded out automatically via just custom FPC. No sense trying before we have some suitable flip chip process tested, though.

Diffraction Limited

An Open Source Motorized XYZ Micro-Manipulator - Affordable sub µm...

If/when I get to it, my plan was for photolitho. I've resurrected my direct-write litho machine (half built, ordered more components to finally finish it). Probably a thick/sturdy resist like SU8, something like that

1

yeah it'd just have to shield that from the nickel spheres or while pillars are grown on the pads.

Playing with some different shapes for the tape for run 2. The ones where we don't touch the corners on a skew are about .6mm clearance. I tried a few different shapes and I think these are pretty close to what we would be wanting. I am still not sure what we can actually get manufactured, but now at least have a baseline I can make some prints from.

1

1

Hey all, A bunch more cob have been made. Unfortunately it seems like JLC has made a bunch of bad boards before we noticed, not sure what we can/will do in the short term, but hopefully a few of you will be seeing more cob sooner than later. Some are to be shipped Mon I believe. I believe the boards are: @Greg @Tim Edwards @RebelMike @Trevor Peyton @Simi

2

Awesome, thanks!

1

Any advice on where to buy mezzanine "receiving" connectors, if I want to avoid buying from China (for tax reasons of avoiding tax hurdles)? (edited)

Hirose might have something compatible. DF40 maybe.

1

RebelMike started a thread. 2026-06-14 9:23 p.m.

After testing some different options for packaging my samples (including the ceramic carriers I posted some weeks ago), I eventually decided for CoB, too, but homemade:

12:48 p.m.

Working like a charm. PCB designs and communication software will come online in the next days. Measurements can finally begin

(edited)

7

3

1

Thorben

Working like a charm. PCB designs and communication software will come online in the next days. Measurements can finally begin

(edited)

I look forward to hearing about it!

1

Andrew Wingate

Oh haha, yes, that would be @Lauri I think the biggest difference is there was a v1 that used some multiplexers that could not be sourced easily. The second version used new ones that were more readily available. You're referring to this thing yes? -# I should get better about sharing pictures, isn't that right @kris ;)

Hey I doubt it matters for this, but if you want, here's some PIO code for driving those CH446Qs. I probably hold the record for most time spent worrying about those chips and RP2350s so if you have any questions about weird edge cases and stuff, lmk.

JumperlOS/src/ch446.pio.h at main · Architeuthis-Flux/JumperlOS

The new Jumperless V5 firmware / operating system. Contribute to Architeuthis-Flux/JumperlOS development by creating an account on GitHub.

1

5:19 a.m.

(idk @Tim 'mithro' Ansell came by my discord to let me know about this so I figured I'd offer my services if you need them)

Architeuthis Flux

Hey I doubt it matters for this, but if you want, here's some PIO code for driving those CH446Qs. I probably hold the record for most time spent worrying about those chips and RP2350s so if you have any questions about weird edge cases and stuff, lmk.

Awesome! Thanks! As far as I understand @Lauri already has them programmed and being used currently. Here's an example of a test. For those at home: It tests the esd diode on the io pins by putting voltage on gnd and testing the volage drop. Also checks for shorts to neighboring pins. A picture is taken There is a rendered result you can see here.

2

BreakingTaps

interesting approach to avoid wire bonding (from https://opg.optica.org/oe/fulltext.cfm?uri=oe-34-11-20833)

That is super cool!

Thorben started a thread. 2026-06-24 7:46 a.m.

Thanks to everyone who helped me get my SRAM chips tested! The COB boards work great (enough of them, anyway), the breakout board works great, and I was able to confirm read and write operation of all three of the 3.3V SRAM macros (256, 512, and 1024 byte) up to 50MHz. More extensive and exhaustive testing will be done, but getting a quick answer as to whether the 3.3V SRAMs are viable for the next tapeout was key.

7

5

Tim Edwards

Thanks to everyone who helped me get my SRAM chips tested! The COB boards work great (enough of them, anyway), the breakout board works great, and I was able to confirm read and write operation of all three of the 3.3V SRAM macros (256, 512, and 1024 byte) up to 50MHz. More extensive and exhaustive testing will be done, but getting a quick answer as to whether the 3.3V SRAMs are viable for the next tapeout was key.

That's awesome!! Thanks for all your work!

woo! great news, cheers for making the macros and testing them!